A limitation in element downsizing in an LSI manufacturing process which begins to be realized in these days forces a three dimensional packaging technology to be focused on as one of the techniques for a higher integration. In the three dimensional packaging technology, LSI chips are stacked in a vertical direction to increase the number of the elements per unit area. In order to achieve this three dimensional packaging, an electric packaging technology with regard to the way that the electric signals between the stacked LSI chips are connected is essential. The electric connection between the LSI chips which has been proposed and performed actually so far is a wire bonding method using a metal thin wire for the connection.
Since the wire bonding has been employed in a two dimensional packaging for a long time and has a enormous accumulation of the technologies, it can be applied relatively easily to the three dimensional packaging technology. Nevertheless, it is required, for connecting the signals between the LSI chips by the wire bonding method, that a signal is drawn out first to the circumferential part of an LSI chip from which then a connection is made to the circumferential part of the target LSI using a metal thin wire and then further drawn using the wiring in the LSI chip into the place where the relevant signal is required within the target LSI. Accordingly, the wire bonding method requires to secure a region for the wire bonding in the circumference of the LSI chip, which leads to a problem involving an increase in the packaging area as well as an elongation of the signal transmission path. In addition, the number of the signal paths between LSI chips is limited by the number of the bonding terminals capable of being provided around the LSI chips.
Recently, a silicon through electrode (TSV (Through silicon via)) method (see Non Patent Literature 1) as an alternative means for electric connection between LSI chips became a focus of attention. In the TSV method, a direct connection of the circuit between the LSI chips is made by using a TSV which is a wiring in the vertical direction through stacked LSI chips instead of allowing an electric signal to go through a wire bonding outside of an LSI chip to obtain an electric connection. It is expected that the problems described above with regard to the wire bonding method are solved by means of wiring between LSI chips using the TSV.
As one of challenges for allowing the TSV method to become a practical one, it is exemplified that a fine hole (via) having a high aspect ratio is embedded within a short period with a conductive material having a high conductivity. While use of a copper as a high conductivity embedding material for a TSV is investigated (see Non Patent Literature 2), it requires, when achieved with copper plating, a time period as long as 2 hours or longer, which should be reduced substantially. In addition to the copper, those which are investigated for use as embedding materials are poly-silicon, tungsten, silver and the like (for example, see Patent Literature 1, Non Patent Literature 3). Comparison between these embedding materials is shown in Table 1.
TABLE 1PolysiliconWCuAgConductivity4.0 × 1041.89 × 1055.96 × 1056.3 × 105(Ω−1cm−1)WiringCVDCVDPlatingPrintingformationmethodPretreatmentSiNWNSi/SiN,Not required(Barrier film(CVD)Ti/TiN,formation)Ta/TaN,(Sputtering orCVD)PretreatmentNot requiredWCuNot required(Seed layer(CVD)(CVD)formation)RemarksBecause ofYield isPost heatstrategyproblematictreatment ismaterial,(voids tend torequired.stableoccur.)Migrationavailabilityoccurs.is notexpected.
Other than these, those which are investigated for use as embedding materials are conductive polymers. The conductive polymers can be obtained from enormous sources and can be used in a process involving an ambient temperature/atmospheric pressure such as application which can advantageously be conducted at a low cost, while they have problematically low conductivities.
On the other hand, a method was reported, aiming at application to catalyst support, immunological diagnostic marker particle and the like, in which the reaction mechanism shown below is employed to conduct a simultaneous precipitation of silver and polypyrrole which is one of the conductive polymers (see Non Patent Literature 4, 5).

Using this method, it is possible to fill a via in a simple procedure with a material having a higher conductivity when compared with conductive polymers.
Nevertheless, the material obtained by this method also failed to achieve a sufficiently high conductivity which should be possessed by a filling material for the TSV, and a problematically high manufacturing cost is still associated because a relatively non-noble metal such as a copper cannot be used.
While Patent Literatures 2 and 3 disclose other methods for manufacturing conductive polymer-metal complexes, none of these Patent Literatures suggest the precipitation of the complex assisted by irradiation of a light and the like.
It is also possible, if such a satisfactorily conductive complex can be formed into thin layers by a simple operation, to provide a novel material which has the both properties of a polymer and a metal and which is suitable to various application. As used herein, a “thin layer” means a fine particle as well as a fine wire by regarding the fine particle and the fine wire as some kinds of thin layers resulting from reducing the areas while keeping the thicknesses constant.
Moreover, if a conductive polymer-metal complex having a satisfactory conductivity is given, and also if it has not only a property similar to that of an existing conductive body such as a metal but also an ability of adhering such a complex strongly by a simple operation onto various substrates usually posing a difficulty in adhering a conductive body such as PTFE (polytetrafluoroethylene), its applicability may dramatically be widened.
On the other hand, a hole having a high aspect ratio such as a via having a small diameter, when being filled with a conductive substance such as a metal, requires a complicated processing such as a procedure for ensuring the first entrance of a processing fluid into the hole, such as a transient reduction in pressure. On the other hand, an electrolytic plating method which is a conventional technique employed frequently for filling a hole such as a via with a metal requires an additional step for forming a seed layer (usually copper) inside the via usually by a non-electrolytic technique such as PVD. If such a hole is made, it fails usually to be in a completely cylindrical form, and protrusions and recesses are formed in ring forms. In such a form, it is difficult to form the seed layer uniformly inside of the via and the number of fabricating processes increases problematically for achieving the inside of the via which is close to a complete cylinder. Thus, a method for overcoming such a difficulty and filling the inside of the via with a conductive material simply and surely is demanded, as well as a processing material employed for such a filling process.